1. Field of the Invention
The present invention relates to a method of and an apparatus for inspecting semiconductor devices such as semiconductor integrated circuits and semiconductor memory devices, and more particularly to an inspection method and an inspection apparatus for semiconductor devices by which an increased number of semiconductor devices can be inspected simultaneously.
2. Description of the Related Art
When a semiconductor device is inspected upon manufacture or delivery, usually a semiconductor tester and the semiconductor device to be inspected are connected to each other through a probe card or a test board. Then, a predetermined inspection signal is applied to each pad or each pin for an input signal of the semiconductor device under the inspection, and a signal at each pad or each pin for an output signal of the semiconductor device then is detected. A semiconductor device of the inspection object may be referred to also as DUT (Device Under Test).
In the field of semiconductor devices, a terminology is sometimes used in different manners depending upon whether a semiconductor device is not packaged as yet or is packaged already in such a manner that, for the semiconductor device before packaged, a representation xe2x80x9cto connect to a pad with a probe card usedxe2x80x9d is used, but for the semiconductor device after packaged, another representation xe2x80x9cto connect to a pin with a test boardxe2x80x9d is used. In the following description, however, pads and pins of semiconductor devices are generally referred to as terminals. Also the probe card for connecting a semiconductor device of the inspection object to a tester is used to include a test board.
In inspection of a semiconductor device, it is requested to minimize the inspection time. To this end, it has been attempted to inspect a plurality of semiconductor devices simultaneously. FIG. 1 shows a basic configuration for inspecting a plurality of semiconductor devices simultaneously with a single tester used.
Tester 61 for inspecting semiconductor devices in accordance with a test program includes a plurality of drivers 62 each for applying a predetermined signal to a terminal 65 for an input signal of semiconductor device 64 to be inspected. Each of semiconductor devices 64 has a plurality of terminals 65 each for an input signal. Tester 61 and semiconductor devices 64 are connected to each other through probe card 63. One driver 62 in tester 61 corresponds to one terminal 65, and therefore, a number of drivers 62 greater than the total number of input terminals 65 of the semiconductor devices 64 to be inspected are prepared.
After all, in the configuration described above, a number of drivers equal to the total number of terminals for an input signal of semiconductor devices to be inspected simultaneously must be prepared in the tester. Therefore, the configuration described has a problem in that the tester has a large-scale configuration. Further, the number of the drivers that are provided in the tester limits the number of semiconductor devices that can be inspected simultaneously. Therefore, the configuration has another problem in that the number of simultaneously inspected semiconductor devices cannot be increased very much.
It is generally considered that semiconductor devices that are inspected simultaneously are of the same type. Thus, Japanese Patent Laid-Open No. 11-231022 (JP, 11231022, A) discloses an apparatus wherein a signal from a driver of a tester is branched in a probe card and supplied in parallel to a plurality of semiconductor devices to be inspected simultaneously as seen from FIG. 2. A wiring scheme by which a signal from a driver is branched and supplied in parallel to a plurality of semiconductor devices is called common drive wiring, and a driver used in such common drive wiring is called a common driver.
In the configuration shown in FIG. 2, three terminals 65a to 65c, and 65d to 65f for an input signal are respectively provided for each of a plurality of semiconductor devices 64a, 64b. The output of driver 62a from among the drivers in tester 61 is connected to terminal 65a of semiconductor device 64a, and the output of driver 62d is connected to terminal 65d of another semiconductor device 64b. However, the output of driver 62b is branched at branching point 66a in probe card 63 and supplied to terminal 65e of semiconductor device 64b. Similarly, the output of driver 62c is branched at branching point 66b in probe card 63 and supplied to terminal 65c of semiconductor device 64a and terminal 65f of semiconductor device 64b. Since the output of each of drivers 62b, 62c is branched and connected to a plurality of terminals for an input signal, drivers 62b, 62c are common drivers.
Such a configuration as described above includes a driver that takes charge of a plurality of terminals and therefore allows a greater number of semiconductor devices to be inspected with a small number of drivers used.
This configuration, however, has a problem in that, if one of semiconductor devices inspected simultaneously has a defect such as leak or a short-circuit at an input terminal, inspection of the remaining normal semiconductor devices is disabled. Where the input terminal of a semiconductor device to be inspected has a MOS (metal-oxide-semiconductor) transistor configuration or a CMOS (complementary MOS) configuration, it is considered that the input resistance of the input terminal is equal to or higher than 0.5 Mxcexa9, typically equal to or higher than approximately 3 Mxcexa9. Therefore, the drivers in a tester are so configured that the current driving capacity thereof may conform to the input resistance. Here, if leak of 100 xcexa9 or less when converted into an input resistance for dc, for example, occurs with one of a plurality of input terminals to which a signal branched from a driver is applied, then a normal signal voltage is not applied to the normal input terminals either. This disables inspection of a normal semiconductor device as well.
This is described in connection with the example shown in FIG. 2. It is assumed here that semiconductor device 64a is a non-defective unit and semiconductor device 64b is a defective unit in that leak occurs with input terminal 65e thereof. Terminal 65e with which leak occurs and terminal 65b of semiconductor device 64a of a non-defective unit are connected in parallel to driver 62b. Therefore, when terminals 65b, 65e are driven by driver 62b, because of the leak at terminal 65e, a regular signal voltage is not applied to normal terminal 65b either, and also semiconductor device 64a of a non-defective unit cannot be inspected normally.
As a countermeasure to solve the problem described above where a signal from a driver is branched and applied to a plurality of input terminals, it is attempted to insert a resistor of approximately several hundreds ohms between a branching point and each input terminal after a signal from a driver is branched in a probe card as seen in FIG. 3. The configuration shown in FIG. 3 is a modification to the configuration shown in FIG. 2 in that resistors 67 of approximately several hundreds ohms (600 xcexa9, for example) are inserted between branching point 66a and terminal 65b, between branching point 66a and terminal 65e, between branching point 66b and terminal 65c, and between branching point 66b and terminal 65f. 
Although this configuration is effective for inspection of a semiconductor device whose clock frequency is comparatively low such as approximately 10 MHz or less, it cannot be used for inspection of a semiconductor device whose clock frequency is higher than 30 MHz. The reason is that, since the input capacitance of each input terminal of a semiconductor device to be inspected is typically 5 pF and provides a time constant of approximately 3 ns together with the inserted register (typically having a resistance of approximately 600 xcexa9), the application timing of the signal to the input terminals is delayed as much and the waveform of the signal applied thereto is distorted. Further, the dispersion in input capacitance disperses the delay time itself for each terminal.
Also with the circuit configuration shown in FIG. 2 or FIG. 3, a signal to which a delay or distortion of the waveform is extremely unfavorable like a reference clock which determines an operation timing of a semiconductor device is supplied to a clock input terminal without being branched from a driver. If some delay occurs with a certain data input terminal as described above, the signal is not latched correctly at the data input terminal when the latch operation is synchronized to the clock signal supplied to the clock input signal. Further, extreme distortion of a signal renders operation of the semiconductor device unstable as well.
FIG. 4 is a diagram illustrating a disadvantage where a waveform suffers from some delay or distortion. Waveform b is a waveform to be latched at a rising edge of waveform a, and it is assumed here that waveform b falls prior to a rising edge of waveform a. Also it is assumed that a resistor is interposed between the driver that outputs waveform b and a terminal of a semiconductor device to be inspected to which waveform b is inputted. Furthermore, it is assumed that the threshold voltage of the latch is just equal to one half power supply voltage Vcc, and consequently, it is discriminated that the input voltage has the xe2x80x9cHxe2x80x9d (high) level when it is equal to or higher than Vcc/2, but the input voltage has the xe2x80x9cLxe2x80x9d (low) level when it is lower than Vcc/2. The solid line curve of waveform b indicates a waveform when no resister is interposed (i.e., waveform at the output point of the driver) and a broken line indicates a waveform at the input terminal of the semiconductor device when the resistor is inserted as seen in FIG. 3. As seen from FIG. 4, where a resistor is connected to the driver which outputs waveform b, waveform b still remains at the xe2x80x9cHxe2x80x9d level at the point of time of the rising edge of waveform a, and therefore, the semiconductor device cannot latch a signal correctly.
In recent years, the clock frequency of a semiconductor memory device, for example, has raised from 66 MHz to 100 MHz and further to 250 MHz, and utilization also of a higher clock frequency is proceeding steadily. Also the bus frequency of a microprocessor has been and is raised similarly. Thus, the delay caused by an inserted resistor restricts the number of simultaneously inspected semiconductor devices of the type described and significantly disturbs augmentation in efficiency of the inspection.
With the conventional inspection methods described above, as the operation speed of a semiconductor device increases, it becomes more difficult to increase the number of semiconductor devices which can be inspected simultaneously without increasing the required number of drivers in a tester while a defect of one of semiconductor devices inspected simultaneously is prevented from having a bad influence on the other normal semiconductor devices.
It is an object of the present invention to provide an inspection method for a semiconductor device by which an increased number of semiconductor devices can be inspected simultaneously without increasing the number of drivers in a tester even where the semiconductor devices of the inspection object are of the type which operates at a high speed.
It is an object of the present invention to provide an inspection apparatus for a semiconductor device by which an increased number of semiconductor devices can be inspected simultaneously without increasing the number of drivers in a tester even where the semiconductor devices of the inspection object are of the type which operates at a high speed.
In the present invention, when a common drive wiring line is used to branch a signal from a driver so that the signal is supplied in parallel to a plurality of input terminals through respective resisters, a capacitor is connected in parallel to each resistor. This simple circuit configuration wherein a capacitor is connected in this manner can suppress delay or distortion of a signal applied to the input terminal even where a resistor is inserted in the common drive wiring line. As a result, a large number of semiconductor devices whose clock frequency is higher than 30 MHz can be inspected simultaneously.
The resistor is used to prevent a defect like a leak defect, which may incidentally occur with one of semiconductor devices connected to the common drive wiring line, from having an influence on the other semiconductor devices, and acts to suppress overcurrent which may flow due to such leak defect. Accordingly, in the present invention, the resistor may be replaced by any current limiting element such as a thermistor having a positive temperature coefficient or a constant current element which makes use of a threshold value-current characteristic of a junction field effect transistor (JFET), for example. Also a resistor is included in the criterion of the current limiting element in the present invention.
Where a resistor is used as the current limiting element, the resistance value of the resistor is determined suitably in accordance with the dc input resistance value or the input capacitance value of the input terminal of the semiconductor device to be inspected. However, where the input terminals of the semiconductor device have a MOS transistor configuration or a CMOS configuration, for example, and have a dc input resistance value equal to or higher than 3 Mxcexa9, the resistance value of the resistor is set within the range from 50 xcexa9 to 1 kxcexa9, more preferably within the range from 50 xcexa9 to 200 xcexa9.
Meanwhile, preferably the capacitance value of the capacitor connected in parallel to the resistor is equal to or higher than the input capacitance of each input terminal of the semiconductor device to be inspected. More strictly, the capacitance value of the capacitor preferably is equal to or higher than an input capacitance value (a designed value or a value on a catalogue, for example) of the input terminal to be connected thereto when the terminal is normal, and more preferably is equal to or higher than 1.5 times the input capacitance value. Since the input terminals of a MOS transistor configuration or a CMOS configuration usually have an input capacitance value of 3 to 5 pF although they have somewhat different input capacitance values before and after the semiconductor device is packaged, the capacitance value of the capacitor connected in parallel to the resistor preferably is equal to or higher than 5 pF, more preferably is equal to or higher than 7 pF, and further more preferably is equal to or higher than 10 pF. However, if the capacitance value is excessively high, then the volume of the capacitor may be so large that it may possibly be difficult to accommodate a required number of capacitors in a probe card or a test board. Further, where leak current at an input terminal of a semiconductor device of the inspection object is very large due to a defect, this unfavorably provides a capacitive load to the driver of the tester. The upper limit to the capacitance value of the capacitor preferably is equal to or lower than 10 times the input capacitance, for example, and more preferably is equal to or lower than 50 pF.
In the present invention, it is possible to use an element having a variable resistance value as the resistor or current limiting element. Further, it is possible to use an element having a variable capacitance value as the capacitor that is connected in parallel to the resistor or current limiting element. Use of such a variable resistor and/or a variable capacitor allows selection of an optimum resistance value and/or an optimum capacitance value in accordance with an electric characteristic of the input terminals of the semiconductor device to be inspected, a clock frequency or the driving capacity of the driver.
In the present invention, the number of branches from one driver in the tester by the common drive wiring line is not limited to 2 but is adjusted suitably in accordance with the number of semiconductor devices to be inspected simultaneously or with some other parameter. The number of branches may be three, four or more, for example.
The semiconductor device to which the present invention can be applied suitably is a semiconductor device such as a semiconductor memory device, a microprocessor or an ASIC (application specific integrated circuit) whose driving clock or reference clock has a frequency equal to or higher than 10 MHz, typically equal to or higher than 50 MHz. A semiconductor memory device, a microprocessor or an ASIC whose reference clock has one of frequencies of 66 MHz, 100 MHz and 133 MHz, for example, is applicable to this. The driving clock or the reference clock here signifies a clock signal that is supplied as a reference to a timing for fetching or outputting of a signal to the semiconductor device. According to the present invention, a plurality of semiconductor devices can be inspected simultaneously through the common drive wiring line even where the clock frequency for the semiconductor devices is 250 MHz, for example.
Furthermore, the present invention is suitably applied also to a semiconductor device for which it is required that the rise time or the fall time of a signal is equal to or shorter than 10 ns, typically equal to or shorter than 5 ns. The time required for an input voltage to rise from its 10% value to its 90% value is called rise time and the time required for an input voltage to fall from its 90% value to its 10% value is called fall time in accordance with a common custom in the pertaining field.
The above and other objects, features, and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate examples of preferred embodiments of the present invention.